Method And System For Gain Control And Power Saving In Broadband Feedback Low-Noise Amplifiers

ABSTRACT

Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include selectively enabling one or more of a subset and all of plurality of gain stages in the low noise amplifier. A feedback resistance coupled across the plurality of gain stages may be adjusted. A gain of each of the plurality of gain stages may be binary weighted. One or more pairs of switching transistors may selectively enable the one or more of the plurality of gain stages. The feedback resistance may include a plurality of individually addressable resistors. The adjustment of the feedback resistance may include switching one or more of a plurality of switching transistors, where one of the plurality of transistors may be connected in parallel with each of the individually addressable resistors. The gain stages may be controlled in parallel, and/or may be digitally controlled.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to, claims priority to, and claims thebenefit of U.S. Provisional Application Ser. No. 60/895,698, filed onMar. 19, 2007, which is incorporated herein by reference in itsentirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[Not Applicable]

FIELD OF THE INVENTION

Certain embodiments of the invention relate to signal amplification.More specifically, certain embodiments of the invention relate to amethod and system for gain control and power saving in broadbandfeedback low-noise amplifiers.

BACKGROUND OF THE INVENTION

As mobile, wireless, and/or handheld portable devices increasinglybecome multifunctional, “all-in-one,” communication devices, thesehandheld portable devices integrate an increasingly wide range offunctions for handling a plurality of wireless communication services.For example, a single handheld portable device may enable Bluetoothcommunication, cellular communication and/or wireless local area network(WLAN) communications.

Much of the front end processing for wireless communications services isperformed in analog circuitry. Front end processing within a portabledevice may comprise a range of operations that involve the reception ofradio frequency (RF) signals, typically received via an antenna that iscommunicatively coupled to the portable device. Receiver tasks performedon a received RF signal may include demodulation, filtering, and analogto digital conversion (ADC), for example. Noise considerations may beimportant since the strength of the received RF signal may be low. Theresulting front-end processed signal may be referred to as a basebandsignal. The baseband signal typically contains digital data, which maybe subsequently processed in digital circuitry within the portabledevice.

Front end processing within a portable device may also includetransmission of RF signals. Transmitter tasks performed on a basebandsignal may include digital to analog conversion (DAC), filtering,modulation, and power amplification (PA), for example. The poweramplified RF signal is typically transmitted via an antenna that iscommunicatively coupled to the portable device by some means. Theantenna utilized for receiving an RF signal at a portable device may ormay not be the same antenna that is utilized for transmitting an RFsignal from the portable device.

One limitation in the inexorable march toward increasing integration ofwireless communications services in a single portable device is that theanalog RF circuitry for each separate wireless communication service maybe implemented in a separate integrated circuit (IC) device (or chip).The increasing chip count may limit the extent to which the physicaldimensions of the portable device may be miniaturized. Thus, theincreasing integration may result in physically bulky devices, which maybe less appealing to consumer preferences. The chip count may be furtherincreased due to the need to replicate ancillary circuitry associatedwith each RF IC. For example, each RF IC may require separate low noiseamplifier (LNA) circuitry, separate PA circuitry, and separate crystaloscillator (XO) circuitry for generation of clocking and timing signalswithin each RF IC. Similar replication may occur for digital IC devicesutilized for processing of baseband signals from each separate wirelesscommunication service.

Along with an increasing IC component count, there may also be acorresponding rise in power consumption within the portable device. Thismay be undesirable due, for example, to increased operating temperature,and reduced battery life between recharges.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for gain control and power saving in broadbandfeedback low-noise amplifiers, substantially as shown in and/ordescribed in connection with at least one of the figures, as set forthmore completely in the claims.

Various advantages, aspects and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an exemplary mobile terminal,which may be utilized in connection with an embodiment of the invention.

FIG. 2 is a block diagram illustrating an exemplary FM receiver frontend, in accordance with an embodiment of the invention.

FIG. 3 is a block diagram illustrating an exemplary low noise amplifiercircuit, in accordance with an embodiment of the invention.

FIG. 4 is a block diagram illustrating an adjustable feedback resistancecircuit, in accordance with an embodiment of the invention.

FIG. 5 is a flow diagram illustrating an exemplary broadband low noiseamplifier control process, in accordance with an embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system forgain control and power saving in broadband feedback low-noiseamplifiers. Exemplary aspects of the invention may comprise controllinggain, power and/or a noise figure by selectively enabling one or more ofa plurality of gain stages by activating one or more of a plurality ofpairs of switching transistors. Each of the gain stages may comprisecomplementary inverter pairs, with the gain of each of the gain stagesbinary weighted and stored in a lookup table. A feedback resistancecoupled across the gain stages may be adjusted, and may comprise aplurality of individually addressable resistors, with the resistancebinary weighted and stored in a lookup table. The adjusting of thefeedback resistance may comprise switching one or more of a plurality ofswitching transistors, each connected in parallel with one of theindividually addressable resistors, which may shunt one or more of theindividually addressable resistors.

FIG. 1 is a block diagram illustrating an exemplary mobile terminal,which may be utilized in connection with an embodiment of the invention.Referring to FIG. 1, there is shown mobile terminal 150 that maycomprise an RF receiver 153 a, an RF transmitter 153 b, a coupler 152, adigital IF processor 159, a processor 155 and a memory 157. An antenna151 may be communicatively coupled to the coupler 152.

The RF receiver 153 a may comprise suitable circuitry, logic, and/orcode that may enable processing of received RF signals. The RF receiver153 a may enable receiving of RF signals in frequency bands utilized byvarious wireless communication systems, such as Bluetooth, FM, WLAN,GSM, and/or WCDMA, for example.

The coupler 152 may comprise suitable circuitry, logic, and/or code toenable coupling of the RF receiver 153 a and the RF transmitter 153 b tothe antenna 151. In this manner, a single antenna may be utilized fortransmitting and receiving RF signals.

The digital IF processor 159 may comprise suitable circuitry, logic,and/or code that may enable processing and/or handling of basebandsignals. In this regard, the digital baseband processor 159 may processor handle signals received from the RF receiver 153 a and/or signals tobe transferred to the RF transmitter 153 b for transmission via awireless communication medium. The digital baseband processor 159 mayalso provide control and/or feedback information to the RF receiver 153a and to the RF transmitter 153 b, based on information from theprocessed signals. The digital baseband processor 159 may communicateinformation and/or data from the processed signals to the processor 155and/or to the memory 157. Moreover, the digital baseband processor 159may receive information from the processor 155 and/or the memory 157,which may be processed and transferred to the RF transmitter 153 b fortransmission to the wireless communication medium.

The RF transmitter 153 b may comprise suitable circuitry, logic, and/orcode that may enable processing of RF signals for transmission. The RFtransmitter 153 b may enable transmission of RF signals in frequencybands utilized by various wireless communications systems, such asBluetooth, Zigbee, FM, WLAN, WiMax, GSM and/or WCDMA, for example.

The processor 155 may comprise suitable circuitry, logic, and/or codethat may enable control and/or data processing operations for the mobileterminal 150. The processor 155 may be utilized to control at least aportion of the RF receiver 153 a, the RF transmitter 153 b, the digitalbaseband processor 159, and/or the memory 157. In this regard, theprocessor 155 may generate at least one signal for controllingoperations within the mobile terminal 150.

The memory 157 may comprise suitable circuitry, logic, and/or code thatmay enable storage of data and/or other information utilized by themobile terminal 150. For example, the memory 157 may be utilized forstoring processed data generated by the digital baseband processor 159and/or the processor 155. The memory 157 may also be utilized to storeinformation, such as configuration information, that may be utilized tocontrol the operation of at least one block in the mobile terminal 150.For example, the memory 157 may comprise information necessary toconfigure the RF receiver 153 a to enable receiving RF signals in theappropriate frequency band.

FIG. 2 is a block diagram illustrating an exemplary FM receiver frontend, in accordance with an embodiment of the invention. Referring toFIG. 2, there is shown FM receiver front end 200 comprising amplifiers210 and 226, a mixer 212, an intermediate frequency local oscillator (IFLO) 214, a bandpass filter (BPF) 216, an analog to digital converter(ADC) 218, an FM demodulator 220, a digital to analog converter (DAC)224 and a digital IF processor (DIP) 222.

The amplifiers 210 and 226 may comprise suitable circuitry, logic,and/or code that may be adapted to amplify input signals and output theamplified signals. The amplifier 210 and/or the amplifier 226 may be alow noise amplifier (LNA). A LNA may be utilized in instances where thesignal to noise ratio (SNR) may be relatively low, such as, for example,RF signals received by an antenna. The amplifiers 210 and 226 may alsobe variable gain amplifiers, where the gain control may be under theprogrammable control of a processor, such as the DIP 222.

The mixer 212 may comprise suitable circuitry, logic, and/or code thatmay be adapted to receive as inputs two signals, and generate an outputsignal, which may be a difference of the frequencies of the two inputsignals and/or a sum of the frequencies of the two input signals. Themixer 212 may receive as inputs, the output signal generated by theamplifier 210, and the output signal generated by the IF LO 214. Theoutput of the mixer 212 may be communicatively coupled to the BPF 216.

The IF LO 214 may comprise suitable circuitry, logic, and/or code thatmay be adapted to output a signal of a specific frequency, either presetor variable under external control, where the external control may be avoltage. The latter type may be referred to as a voltage controlledoscillator (VCO). A VCO control voltage may be under programmablecontrol of a processor, such as the DIP 222. In another embodiment ofthe invention the IF LO 214 may comprise a discrete digital frequencysynthesizer (DDFS).

The BPF 216 may comprise suitable circuitry, logic, and/or code that maybe adapted to selectively pass signals within a certain bandwidth whileattenuating signals outside that bandwidth.

The FM demodulator 220 may comprise suitable circuitry, logic, and/orcode that may enable demodulation of the digital IF FM signal generatedby the ADC 218. The demodulation of the digital IF FM signal maygenerate a baseband signal which may comprise the original informationsignal intended for the FM receiver front end 200, such as audio signalsor other information embedded into the FM signal. The down-conversion ofthe digital IF signal to the digital baseband signal may utilizedecimation filters where the input frequency of the decimation filtermay be a multiple of the output frequency of the decimation filter.

The DIP 222 may comprise suitable circuitry, logic, and/or code that maybe adapted to control the FM demodulator 220, the IF LO 214 and theamplifiers 210 and 216. The DIP 222 may extract desired data from the FMsignal received by the amplifier 210, and may control the demodulationof the digitized IF FM signal generated by the ADC 218. The digitalfiltering of the digital samples may utilize, for example, a derotatorthat may use a coordinate rotation digital calculation (CORDIC)algorithm.

The DAC 224 may comprise suitable circuitry, logic, and/or code that mayenable conversion of a digital input signal to an analog output signal.The DAC 224 may receive as an input, the demodulated digital IF signalgenerated by the FM demodulator 220 and may generate an analog outputsignal that may be communicated to the amplifier 226.

In operation, the FM signal, which may have a carrier frequency referredto as f_(FM), may be received by an antenna and communicated to theamplifier 210, where the FM signal may be amplified by the amplifier210, where the gain of the amplifier 210 may be adjusted based on thestrength of the received FM signal. The amplified FM signal may becommunicated to an input of the mixer 212. The output signal of the IFLO 214, which may have a frequency of f_(LO)=f_(FM)+f_(IF) orf_(LO)=f_(FM)-f_(IF), may be communicated to another input of the mixer212, where f_(IF) may be a desired intermediate frequency. The mixer 212may process the two input signals such that the output signal may have afrequency, which may be a sum and/or a difference of the frequencies ofthe two input signals. The mixer 212 output signal may be referred to asan IF signal.

The IF signal may be communicated to the BPF 216, which may be adaptedto pass the desired bandwidth of signals about the IF frequency f_(IF),while attenuating the undesired frequencies in the IF signal. Thefiltered IF signal may be communicated to the ADC 218 where the filteredIF FM signal may be converted to a digital signal. The resulting digitalsignal may then be demodulated by the demodulator 220, and may bedigitally filtered to remove artifacts of the digital down-conversionprocess before being re-converted to an analog signal by the DAC 224.The analog output signal of the DAC 224 may be amplified by theamplifier 226.

FIG. 3 is a block diagram illustrating an exemplary low noise amplifiercircuit, in accordance with an embodiment of the invention. Referring toFIG. 3, there is shown LNA circuit 300 comprising PMOS transistors Q₁,Q₂, Q₅, Q₆, Q₉, Q₁₀, Q₁₃ and Q₁₄, NMOS transistors Q₃, Q₄, Q₇, Q₈, Q₁₁,Q₁₂, Q₁₅ and Q₁₆, bias voltage V_(bias), supply voltages V_(DD) andV_(SS), bias resistance R_(B), feedback resistance R_(FB) and capacitorC. There is also shown input terminals P₁, P₅, P₉, P₁₃, N₄, N₈, N₁₂,N₁₆, V_(IN) and output terminal V_(OUT).

Each vertical column of transistors, such as the PMOS transistors Q1 andQ2 and NMOS transistors Q3 and Q4 may comprise a gain stage of theamplifier, with four stages shown in the exemplary LNA circuit 300. Eachstage may comprise transistors with a specific multiplication factor,determined by transistor size, for example, that may be different fromthe multiplication factors of the transistors in the other stages. Thusthe gain and power level of each stage may differ from the other stages.The invention is not limited to the number of stages shown in FIG. 3,and as such may comprise any number of stages depending on the requiredgain levels and power requirements of the LNA circuit 300.

The source terminals of the PMOS transistors Q₁, Q₅, Q₉ and Q₁₃ may becoupled to the supply voltage V_(DD), and the source terminals of theNMOS transistors Q₄, Q₈, Q₁₂ and Q₁₆ may be coupled to the supplyvoltage V_(SS). The gate terminals of PMOS transistors Q₂, Q₆, Q₁₀ andQ₁₄ may be coupled together and may comprise the input terminal for theLNA circuit 300, denoted by V_(IN) in FIG. 3. The input terminal V_(IN)may be AC coupled to the common gate terminals of the NMOS transistorsQ₃, Q₇, Q₁₁ and Q₁₅ by the capacitor C. A terminal of the bias resistorR_(B) may also be coupled to the common gate terminals of thetransistors Q₃, Q₇, Q₁₁ and Q₁₅, with the other terminal of the biasresistor R_(B) comprising the input terminal V_(bias).

The PMOS transistors Q₁, Q₅, Q₉ and Q₁₃ and the NMOS transistors Q₄, Q₈,Q₁₂, Q₁₆ may comprise switches that may be enabled to activate aparticular stage of the LNA circuit 300. The gate terminals of thetransistors Q₁, Q₅, Q₉, Q₁₃ Q₄, Q₈, Q₁₂ and Q₁₆ may comprise the inputterminals P₁, P₅, P₉, P₁₃, N₄, N₈, N₁₂, N₁₆ and may be biased toactivate the switches. For example, if the gate terminals of PMOStransistor Q₁ and the NMOS transistor Q₄ may be biased in the on state,the first gain stage comprising the transistors Q₂ and Q₃ may beenabled.

The output terminal of the LNA circuit 300, indicated by V_(OUT) in FIG.3, may comprise the common node defined by the drain terminals of thePMOS transistors Q₂, Q₆, Q₁₀ and Q₁₄ and the NMOS transistors Q₃, Q₇,Q₁₁ and Q₁₅. The feedback resistor, R_(FB), may couple the outputterminal, V_(OUT), to the input terminal V_(IN) of the LNA circuit 300,and is delineated between the nodes X and Y. The feedback resistorR_(FB), may be adjustable and is described further with respect to FIG.4.

In operation, bias and supply voltages may be applied to the LNA circuit300 at V_(bias), V_(DD) and V_(SS). The bias voltage V_(bias) may beadjusted to bias the NMOS transistors Q₃, Q₇, Q₁₁ and Q₁₅ at a desiredvoltage, the midpoint between V_(DD) and V_(SS), for example. The inputterminals P₁, P₅, P₉, P₁₃, N₄, N₈, N₁₂, N₁₆ may be biased at appropriatevoltages to activate desired gain stages. For example, if the inputterminals P₁, P₅, P₉, P₁₃ are asserted low and the input terminals N₄,N₈, N₁₂, N₁₆ are asserted high, the transistors Q₁, Q₅, Q₉, Q₁₃ Q₄, Q₈,Q₁₂ and Q₁₆ may be switched on and all four gain stages may be enabled.Thus, in instances where an input signal may be communicated to theinput terminal V_(IN), an amplified version of the input signal may begenerated at the output terminal, V_(OUT).

The gain of the LNA circuit 300 may be adjusted by enabling and/ordisabling gain stages by applying appropriate input voltages at theinput terminals P₁, P₅, P₉, P₁₃, N₄, N₈, N₁₂, N₁₆. A challenge inadjusting the gain of an amplifier may be the variation of the inputimpedance. For an amplifier with resistive feedback, if the outputimpedance of the amplifier transistors may be large compared to thefeedback resistance, which may be typical, the low-frequency inputresistance, R_(i), may be calculated from the following equation:

$R_{i} = \frac{1}{g_{m\; p} + g_{mn}}$

where g_(mp) and g_(mn) are the transconductance values of PMOS and NMOSdevices, respectively. Therefore, for a given current, the inputresistance may remain essentially constant with feedback resistanceR_(FB).

The gain of the LNA circuit 300, utilizing the same assumption, may bedetermined by the following:

$g = {{{- R_{FB}}*\left( {g_{m\; p} + g_{mn}} \right)} = \frac{- R_{FB}}{R_{i}}}$

Thus, the gain may be adjusted by adjusting the feedback resistanceR_(FB), while the input resistance, R₁, may remain constant as shown inthe previous equation.

In this manner, the gain of the LNA circuit 300 may be adjusted eitherby adjusting the feedback resistance R_(FB), or by switching selectedgain stages on or off, which may result in a large range of possiblegain values. The gain of each gain stage may be twice as high as thepreceding stage, and half that of the next stage, thus creating a binaryweighted scheme for the gain stages.

With a plurality of enabled gain stages, the total transconductance maybe considered a sum of the individual transconductances, and highertransconductance may result in higher gain and a lower noise figure.Adjusting the feedback resistance R_(FB), may adjust the gain of the LNAcircuit 300, as described above, but may not affect the power and theinput impedance. The input impedance may be affected by the NMOS andPMOS transconductances of the LNA circuit 300, so by enabling and/ordisabling selected gain stages, the input impedance may be adjusted.Thus, the gain stages may be designed to provide impedance match with aninput device, such as a 50 ohm antenna, for example.

Switching gain stages on and off may change the power usage of the LNAcircuit 300, such that the RF receiver 153 a may utilize less power whendesired. For example, in instances when a large input signal may bepresent, lower gain may be necessary so that gain stages may bedisabled, resulting in reduced power drain.

Exemplary performance parameters comprising gain, noise figure, inputimpedance and power of the LNA circuit 300 may be adjusted by enablingselected gain stages and adjusting the feedback resistance R_(FB). Therange of values utilized to obtain the array of performancecharacteristics may be stored in a lookup table in the memory 157, forexample, described with respect to FIG. 1.

FIG. 4 is a block diagram illustrating an adjustable feedback resistancecircuit, in accordance with an embodiment of the invention. Referring toFIG. 4, there is shown feedback resistance circuit 400 comprising NMOStransistors Q_(R1), Q_(R2), Q_(R3) and Q_(R4) and resistors R₁, R₂, R₃,R₄ and R₅. There is also shown input terminals V_(R1), V_(R2), V_(R3)and V_(R4). The feedback resistance, R_(FB), may be defined as theresistance between the nodes X and Y, which may correspond to the nodesX and Y described with respect to FIG. 3.

In instances where the transistors Q_(R1), Q_(R2), Q_(R3) and Q_(R4) maynot be enabled, or switched on, the feedback resistance R_(FB) betweenthe nodes X and Y, may comprise the series combination of the resistorsR₁, R₂, R₃ R₄ and R₅. The resistance value of each resistor of R₁, R₂,R₃, R₄ and R₅ may be twice that of the next resistor and half that ofthe preceding resistor. For example, R₁ may be 1000 ohms, R₂ may be 500ohms and R₃ may be 250 ohms, thus creating a binary weighted scheme forthe feedback resistance R_(FB).

The node X may comprise one terminal of the resistor R₅ and the otherterminal of the resistor R₅ may be coupled to a terminal of the resistorR₄ and the drain terminal of the transistor Q_(R4). The gate terminalsof the transistors Q_(R1), Q_(R2), Q_(R3) and Q_(R4) may comprise theinput terminals V_(R1), V_(R2), V_(R3) and V_(R4).

The node Y of the feedback resistance circuit 400 may comprise oneterminal of the resistor R₁ and the source terminal of the transistorQ_(R1). The drain terminal of the transistor Q_(R1) may be coupled tothe other terminal of the resistor R₁, a terminal of the resistor R₂ andthe source terminal of the transistor Q_(R2). This connection scheme,with the drain and source terminals of an NMOS transistor each coupledto a terminal of a resistor, in series with the next resistor/transistorpair, is repeated for resistors R₂ to R₄. The invention is not limitedto the number of resistors illustrated in FIG. 4. Accordingly, anynumber of resistor/transistor pairs may be utilized depending on thedesired resistance values and die size constraints, for example.

In operation, the input terminals V_(R1), V_(R2), V_(R3), and V_(R4) maybe utilized to adjust the resistance of the feedback resistance circuit400. The input terminals V_(R1), V_(R2), V_(R3) and V_(R4) may beutilized to bypass the associated resistor R₁, R₂, R₃ and/or R₄ in thecircuit. For example, applying a high signal to V_(R1) may switch on thetransistor Q_(R1), effectively bypassing the resistor R₁. The type oftransistors utilized for the transistors Q_(R1), Q_(R2), Q_(R3) andQ_(R4) may be selected to result in a minimum drain to source impedance,thus creating a minimum impedance short of a resistor when a giventransistor may be switched on. In this manner, any combination of theseries resistors may be enabled and/or disabled to obtain a desiredresistance.

The multiple resistance values and LNA circuit 300 gain values madepossible by enabling or disabling resistors in the feedback resistancecircuit 400 may be stored in a lookup table in the memory 157, forexample, described with respect to FIG. 1.

FIG. 5 is a flow diagram illustrating an exemplary broadband low noiseamplifier control process, in accordance with an embodiment of theinvention. Referring to FIG. 5, following start step 501, in step 503, aprocessor, such as the digital IF processor 222, may determine thedesired gain, noise figure and power level of the amplifier 210 based ona received FM RF signal. In step 505, the processor 222 may enableappropriate gain stages based on prestored gain values in a lookup tablestored in the memory 157, for example. In step 507, the DIP 222 mayenable appropriate resistors to set an appropriate gain. The gain valuesversus the feedback resistance R_(FB) may also be stored in a lookuptable. In step 509, the input signal may be applied to the amplifier210, and in step 511 an amplified output signal may be generated. Instep 513, if it is desired to adjust the gain, power and/or noisefactor, the process may step back to step 503 to restart the gainadjustment process, and if not may proceed to end step 515.

In an exemplary embodiment of the invention, a method and system aredisclosed for controlling gain, power and/or noise figure by selectivelyenabling one or more of a plurality of gain stages by activating one ormore of a plurality of pairs of switching transistors. Each of the gainstages may comprise complementary inverter pairs Q₂/Q₃, Q₆/Q₇, Q₁₀/Q₁₁and Q₁₄/Q₁₅, with the gain of each of the gain stages being binaryweighted and stored in a lookup table. A feedback resistance, R_(FB),coupled across the gain stages may be adjusted, and may comprise aplurality of individually addressable resistors, R₁, R₂, R₃ and R₄, withthe resistance values being binary weighted and stored in a lookuptable. The adjusting of the feedback resistance may comprise switchingone or more of a plurality of switching transistors, Q_(R1), Q_(R2),Q_(R3) and Q_(R4), each connected in parallel with one of theindividually addressable resistors, which may shunt one or more of theindividually addressable resistors when enabled.

Certain embodiments of the invention may comprise a machine-readablestorage having stored thereon, a computer program having at least onecode section for communicating information within a network, the atleast one code section being executable by a machine for causing themachine to perform one or more of the steps described herein.

Accordingly, aspects of the invention may be realized in hardware,software, firmware or a combination thereof. The invention may berealized in a centralized fashion in at least one computer system or ina distributed fashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware, software and firmware may bea general-purpose computer system with a computer program that, whenbeing loaded and executed, controls the computer system such that itcarries out the methods described herein.

One embodiment of the present invention may be implemented as a boardlevel product, as a single chip, application specific integrated circuit(ASIC), or with varying levels integrated on a single chip with otherportions of the system as separate components. The degree of integrationof the system will primarily be determined by speed and costconsiderations. Because of the sophisticated nature of modernprocessors, it is possible to utilize a commercially availableprocessor, which may be implemented external to an ASIC implementationof the present system. Alternatively, if the processor is available asan ASIC core or logic block, then the commercially available processormay be implemented as part of an ASIC device with various functionsimplemented as firmware.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext may mean, for example, any expression, in any language, code ornotation, of a set of instructions intended to cause a system having aninformation processing capability to perform a particular functioneither directly or after either or both of the following: a) conversionto another language, code or notation; b) reproduction in a differentmaterial form. However, other meanings of computer program within theunderstanding of those skilled in the art are also contemplated by thepresent invention.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the present inventionwill include all embodiments falling within the scope of the appendedclaims.

1-30. (canceled)
 31. A method for signal amplification, the methodcomprising: controlling gain, power and/or a noise figure of a low noiseamplifier by selectively enabling a subset of a plurality of gain stagesin said low noise amplifier; and adjusting a feedback resistance coupledacross said subset of said plurality of gain stages.
 32. The methodaccording to claim 31, wherein a gain of each of said subset of saidplurality of gain stages is binary weighted.
 33. The method according toclaim 31, comprising activating one or more of a plurality of pairs ofswitching transistors for said selectively enabling of said subset ofsaid plurality of gain stages.
 34. The method according to claim 31,wherein said feedback resistance comprises a plurality of individuallyaddressable resistors.
 35. The method according to claim 34, whereinsaid adjusting of said feedback resistance comprises switching one ormore of a plurality of switching transistors, wherein one of saidplurality of transistors is connected in parallel with each of saidindividually addressable resistors.
 36. A method for signalamplification, the method comprising: controlling gain, power and/or anoise figure of a low noise amplifier by selectively enabling one ormore of a plurality of parallel gain stages in said low noise amplifier;and adjusting a feedback resistance coupled across said one or more ofsaid plurality of parallel gain stages.
 37. The method according toclaim 36, wherein a gain of each of said one or more of said pluralityof gain stages is binary weighted.
 38. The method according to claim 36,comprising activating one or more of a plurality of pairs of switchingtransistors for said selectively enabling of said one or more of saidplurality of gain stages.
 39. The method according to claim 36, whereinsaid feedback resistance comprises a plurality of individuallyaddressable resistors.
 40. The method according to claim 39, whereinsaid adjusting of said feedback resistance comprises switching one ormore of a plurality of switching transistors, wherein one of saidplurality of transistors is connected in parallel with each of saidindividually addressable resistors.
 41. A method for signalamplification, the method comprising: controlling gain, power and/or anoise figure of a low noise amplifier by digitally enabling one or moreof a plurality of parallel gain stages in said low noise amplifier; andadjusting a feedback resistance coupled across said one or more of saidplurality of gain stages.
 42. The method according to claim 41, whereina gain of each of said one or more of said plurality of gain stages isbinary weighted.
 43. The method according to claim 41, comprisingactivating one or more of a plurality of pairs of switching transistorsfor said selectively enabling of said one or more of said plurality ofgain stages.
 44. The method according to claim 41, wherein said feedbackresistance comprises a plurality of individually addressable resistors.45. The method according to claim 44, wherein said adjusting of saidfeedback resistance comprises switching one or more of a plurality ofswitching transistors, wherein one of said plurality of transistors isconnected in parallel with each of said individually addressableresistors.
 46. A system for signal amplification, the system comprising:one or more circuits that controls gain, power and/or a noise figure ofa low noise amplifier by selectively enabling a subset of a plurality ofgain stages in said low noise amplifier; and said one or more circuitsadjusts a feedback resistance coupled across said subset of saidplurality of gain stages.
 47. The system according to claim 46, whereina gain of each of said subset of said plurality of gain stages is binaryweighted.
 48. The system according to claim 46, wherein said one or morecircuits enables activation of one or more of a plurality of pairs ofswitching transistors for said selectively enabling of said one or moreof said subset of said plurality of gain stages.
 49. The systemaccording to claim 46, wherein said feedback resistance comprises aplurality of individually addressable resistors.
 50. The systemaccording to claim 49, wherein said one or more circuits enablesswitching one or more of a plurality of switching transistors, whereinone of said plurality of transistors is connected in parallel with eachof said individually addressable resistors.
 51. A system for signalamplification, the system comprising: one or more circuits that controlsgain, power and/or a noise figure of a low noise amplifier byselectively enabling one or more of a plurality of parallel gain stagesin said low noise amplifier; and said one or more circuits adjusts afeedback resistance coupled across said one or more of said plurality ofparallel gain stages.
 52. The system according to claim 51, wherein again of each of said one or more of said plurality of gain stages isbinary weighted.
 53. The system according to claim 51, wherein said oneor more circuits enables activation of one or more of a plurality ofpairs of switching transistors for said selectively enabling of said oneor more of said plurality of gain stages.
 54. The system according toclaim 51, wherein said feedback resistance comprises a plurality ofindividually addressable resistors.
 55. The system according to claim54, wherein said one or more circuits enables switching one or more of aplurality of switching transistors, wherein one of said plurality oftransistors is connected in parallel with each of said individuallyaddressable resistors.
 56. A system for signal amplification, the systemcomprising: one or more circuits that controls gain, power and/or anoise figure of a low noise amplifier by digitally enabling one or moreof plurality of gain stages in said low noise amplifier; and said one ormore circuits adjusts a feedback resistance coupled across said one ormore of said plurality of gain stages.
 57. The system according to claim56, wherein a gain of each of said one or more of said plurality of gainstages is binary weighted.
 58. The system according to claim 56, whereinsaid one or more circuits enables activation of one or more of aplurality of pairs of switching transistors for said selectivelyenabling of said one or more of said plurality of gain stages.
 59. Thesystem according to claim 56, wherein said feedback resistance comprisesa plurality of individually addressable resistors.
 60. The systemaccording to claim 59, wherein said one or more circuits enablesswitching one or more of a plurality of switching transistors, whereinone of said plurality of transistors is connected in parallel with eachof said individually addressable resistors.